The present invention relates to integrated circuits, and more particularly, to a SRAM array having reduced bitline leakage current.
Metal oxide semiconductor (MOS) static random access memory (SRAM) arrays are comprised of an array of SRAM cells. The SRAM cells are read, erased, and written to by means of bitlines (BL) and wordlines (WL). In one common design, the SRAM cells consist of load elements in a flip-flop configuration, together with two select transistors.
FIG. 1 is a schematic circuit diagram of a six-transistor (6T) SRAM cell 101 that is commonly and widely used in SRAM memory arrays. The SRAM cell 101 is known in the art as a 6T SRAM cell. The SRAM cell 101 includes N-type MOS (NMOS) transistors N1 and N2 (hereinafter transistors N1 and N2) coupled between VSS (typically ground) and nodes A and B, respectively. Nodes A and B are further coupled to VDD by pull-up P-type MOS (PMOS) transistors P1 and P2 (hereinafter transistors P1 and P2), respectively. Node A is further coupled to the gates of transistors P2 and N2 and node B is similarly coupled to the gates of transistors P1 and N1.
Information is stored in SRAM cell 101 in the form of voltage levels in the flip-flop formed by the two cross-coupled inverters formed by transistors P1, N1 and P2, N2, respectively. In particular, when node A is at a logic low state (the voltage of node A being approximately equal to VSS), transistor P2 is on (in a low resistance state or conducting) and transistor N2 is off (in a high resistance state or non conducting). When transistor P2 is on and transistor N2 is off, node B is at a logic high state (the voltage of node B is pulled up to approximately VDD). Further, when node B is at a logic high state, transistor P1 is off and transistor N1 is on. When transistor P1 is off and transistor N1 is on, node A is at a logic low state (the voltage of node A is pulled down to approximately VSS). In this manner, SRAM cell 101 remains in a latched state.
Nodes A and B are further coupled to a xe2x80x9cbitlinexe2x80x9d and a xe2x80x9cbitline-notxe2x80x9d by NMOS select transistors N3 and N4 (hereinafter transistors N3 and N4), respectively. The gates of transistors N3 and N4 are coupled to a word line to enable read and write operations, as those skilled in the art will understand.
A read operation is performed by turning on the word line and allowing one side of the SRAM cell to start pulling down on one line of the bitline pair. For example, if node A is low and the word line is pulled high, then a current will flow through select transistor N3 and transistor N1 to ground or Vss.
When node A is low and the word line is low, the SRAM cell 101 has a leakage current 103 that flows from the bitline through the select transistor N3 and transistor N1 down to ground or Vss.
As the size of the SRAM cells decreases, the amount of read current produced by the SRAM cell also decreases, particularly as the supply voltage Vcc is lowered as technology advances. As the amount of read current decreases, the leakage current becomes larger relative to the read current, thereby making it more difficult to accurately read the SRAM cell. Thus, it is desirable to lower the amount of leakage current from each SRAM cell.
One method of solving this problem is to reduce the number of SRAM cells per bitline, thereby reducing the overall amount of leakage current. However, this increases the amount of overhead devices such as sense amplifiers, column multiplexer circuitry, etc. for a given number of SRAM cells.
Another approach is to increase the channel length of the transistors in the SRAM cell. However, this increases the SRAM cell size. Furthermore, effect of this approach is limited, as the transistor devices get smaller.